We have seen set_multicycle_path constraint for timing path within a single clock domain. Now let’s explore multicycle paths with two synchronous clock domains of different frequencies. The SDC command `set_multicycle_path`… Read more »
Back when I gave an introduction to SDC, I brushed upon `set_false_path` statements between clocks. However, now there is a more efficient way of specifying the the clock exceptions in… Read more »
When an asynchronous signal, or a signal from a block clocked by a different clock is received by a synchronous circuit, it is imperative that it is reliably sampled by… Read more »
In digital circuit, the signal is required to be within certain voltage or current limits (logic 0/1 levels) for correct circuit operation. If the signal is within an intermediate range… Read more »
Many a time your chip is overdesigned due to undue pessimism in timing calculations. Pessimism in timing analysis makes it difficult for designs to close timing and it is imperative… Read more »
As we saw in the earlier article on ICG, a gated clock is when you use a logic gate to control or enable to the propagation of clock to certain… Read more »
Minimum pulse width checks are done to ensure that width of the clock signal is wide enough for the cell’s internal operations to complete. i.e. to get a stable output… Read more »
Recovery and removal analysis are done on asynchronous signals like resets. These specify the requirement of these signals with respect to clock.Recovery Time is the minimum required time to the… Read more »
SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF now has the delay numbers derived from these… Read more »
By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that some data is captured only after a specified… Read more »
