What is meant by lint? It was the name originally given to a program that flagged suspicious and non-portable constructs in software programs.
Later this was extended to hardware languages as well for early design analysis. That means rule checks will be applied on the developed RTLs and it helps to identify errors which we would be getting in the upcoming design cycle stages like synthesis etc.This also helps to make sure that during optimization stage, design functionality is not changed. Overall, it points out where the code is likely to have bugs.
One important point about linting is that it checks the cleanness and portability of the HDL code for various EDA tools and not anything related to the actual functionality of the design.
How does it work?
There are some set of rules defined in the lint tool. Rule means a condition that has to be checked on your design. User can enable and disable the required rules as per his requirement. Once these rules are run on the design, and if design source code does not conform to a rule, violation will be reported.
You can have your own policy file (tcl file) specifying the rules to be checked for. Also specify whether you want particular rule check result has to be an error, warning or info.
- Change configuration/Define rule set.
- User can change the configuration settings and modify the rules set by enabling or disabling as per their requirement.
- Invoke tool and Source rules
- Analyse Design
- Generate report
- Differences between simulation and synthesis semantics
- Opportunities to improve simulation performance
- Probable simulation errors
- Chances of matching gate level simulations with RTL simulations
- Coding guidelines
- FSM state reachability and coding issues
- Network and connectivity checks for clocks, resets, and tri-state driven signals
- Module partitioning
- Tool flow issues in the upcoming design cycle stages
- Possible synthesis issues. (eg unintended latches or combo loops)
- Clocks and reset definitions.
- COMBO_LOOP : It reports if there is a combinational loop in the design.
- TERMINAL_STATE : It reports, if a state in a FSM that once entered never reaches to another state via next state assignment.
- COMBO_NBA : It reports NBA reg assignment from a combo block.
- MULTI_DEFINES : It reports, if there are more than one macros with the same name.
- INC_SENS_LIST : If a signal is referenced and not used in the sensitivity list of the block, it reports the failure.
Some of the available tools in the market to do linting and CDC checks are
- Realintent (Ascentlint, IIV,Meridian)
- Most of the formal verification tools (Onespin, IFV etc)
Can we also called this Linting errors as post synthesis simulation mismatch?
Post synthesis simulation mismatches can be reduced by cleaning up the lint errors in the RTL stage.
where do we do linting process in ASIC design flow??
Linting is used at RTL stage by the designer. Before RTL freeze linting should be clean so that there wouldn’t be any surprise during synthesis.
how the linting is useful for any varification engineer?
Hi, Sorry for disturbing.
About lint, whether “generate…endgenerate”structure can pass lint check even it’s synthesizable?
could u pls expain what is diffrence between HAl(cadence) and Lint check(Spyglass)?
are they are same.
in pre-pnr netlist why a combo loop should not exist and what is is a effect of combo loop on back-end.
Helped me a lot to get a brief idea about Linting. Thanks!
A nice brief explanation! Thanks Sini.
Thank You !
This cleared my understanding on lint.. Thank you so much madam..
very nice information…
Please Expecting more on CDC and Synthesis.. Please..
Can you tell me.. What is RTL integration.. What basic knowledge we should have for that. Any progress languages.. Any theory.. Please tell me references..