At lower technology nodes, leakage power is proving to be a major component of power with the lowered supply and threshold voltage. One method to better balance power and timing is using different VT cells in the design.By changing the characteristic like doping of the channels, threshold voltages can be varied.
These are the flavours commonly available.
Low-Vt cells have a lowered threshold voltage. i.e. it has a faster operation, but leakage currents are more.
Standard-Vt cells. These are optimized for power and timing, so have medium leakage and is faster than HVT cells.
High-Vt cells have the highest threshold voltage for device operation in this group. The cells are slower, but due to the higher threshold, leakage is also lower.
In timing critical paths, LVT cells can be used to take advantage of the higher performance. One important point to note is that you need to use the same threshold cells for clock tree to reduce the variations in the clock tree. You can decide on the timing/power requirement of the design, but a standard practice is to reserve SVT cells for clock trees.
what about the variation for these cells in silicon ? Which cells are more prone to variation among SVT ,LVT,HVT ?