Process variation is a naturally occuring variation in the attributes of transistors(length, widths, oxide thickness) when integrated circuits are fabricated. These variations can be:
There can be parameter difference due to process variation between different dies/wafers/lots.
Within a single chip, parameter differeces can arise due to manufacturing.
Sources of Variation
-Impurity concentration densities
-Diffusion depth variation
-Erosion and dishing in CMP process
Changes in these parameters cause characteristics like threshold voltage and RC to vary. This causes a difference in timing of the manufactured transistors. Usually the libraries are characterised for different process corners, to make sure the process variations are accounted for in the design, through historic manufacturing data for the process. However, since the variation can also be within a single chip, we need to allow for the some paths being of different process while doing STA. OCV helps us in defining this variation for the STA tool to use. As mentioned earlier, a derate can be used to specify the effects of variation.
AOCV (Advanced OCV)
OCV characterisation assumes a default length for the path. However, a single cell exhibits a larger variance compared to a group of cells. You really cannot use the same derate for each cell in the path because some of the variation tend to cancel out in the group. In this case OCV leads to an overly pessimistic analysis for larger paths, and overly optimistic analysis for shorter paths. So In AOCV, depth of the path is also consdered while specifying the delay margin.
depth : 1 3 5 7 9 table: 1.2 1.19 1.18 1.16 1.14