Physical Design Flow I : NetlistIn & Floorplanning

This is going to be a series of step-by-step explanation of physical design flow for the novice. I am going to list out the stages from Netlist-GDS in this session. Of course some say synthesis should also be part of physical design, but we will skip that for now.

So, you have completed your RTL, synthesised it and now you have a netlist & constraints. Next comes the physical design part of it;making your design into a representation of the actual geometries you will manufacture. You will do a bunch of stuff here, like floorplanning, placement, CTS, routing, timing closure, physical verification, formal verification etc. The major stages are explained below.

Netlist In
The first stage in physical design flow is reading in the netlist and the constraints to your tool of choice. Let us see what kinds of files we are dealing with here. I have used both Cadence and Synopsys tools extensively, so those are what I will base my examples on. However, every tool uses pretty much the same flow and even the same format files.

    1. Gate Level Netlist
      Once you choose a process and a library, a synthesis tool will translate your RTL into a collection of interconnected logic gates that define the logic. The most common format is verilog. I had seen some VHDL and EDIF designs when I started my career, but I have only really worked with Verilog files.
    1. Standard Cell Library
      In digital design, you have a ready made standard cell library which will be used for synthesis and subsequent layouts. Your netlist will have instantiation of these cells. For digital layout, you need layout and timing abstracts for these cells.

      • Layout Model – An abstract model of the standard cell layout is used instead of the complete layout. This will have PINs defined, so as to facilitate automatic routing by the tool as per your netlist. Synopsys tool ICCompiler use “FRAM” views as a PnR abstract. FRAM view is a cell view that has only the PINs and metal and via blockages defined. This makes sure that the interconnection between the PINs can be routed automatically and that the routing tool will not route over existing metal/via areas thus ruling out any shorts. Cadence EDI tools use LEF views, which again has only the PINs and Obstructions (blockages) defined. LEF is an ascii file, so go ahead and have a read.
      • Timing Model – Tools also need a timing model in the form of a .lib file. ICC takes a .db file, which is generated from a .lib. This liberty format file will have timing numbers for the various arcs in a cell, generally in a look up model. Please note that .libs may also have cell power information.
    1. Technology File
      The rules pertaining to the process you have selected should also be given to the PnR tool. This includes metal widths, spacing, via definitions etc. ICC takes a milkyway techfile format, while EDI tools take a technology LEF file. Please see this post for some details.
  1. Timing Constraints
    SDC files define the timing constraints of your design. You will have the clock definitions, false paths, any input and output delay constraints etc.

These inputs once read in, will get you started with your database.

set search_path "<.db_file_paths>"
set link_library "* std_lib1.db std_lib2.db"
create_mw_lib my_design_lib \
	-technology  \
	-mw_reference_library " \
read_verilog ./my_design.v

The above snippet of code creates a library with the name “my_design_lib”. The .db files are specified using “set link_library” and the paths where they can be found at “set search_path”.


This is the first major step in getting your layout done, and for me this is the most important one.Your floorplan determines your chip quality.At this step, you define the size of your chip/block, allocates power routing resources, place the hard macros, and reserve space for standard cells.Every subsequent stage like placement, routing and timing closure is dependent on how good your foorplan is. In a real time design, you go through many iterations before you arrive at an optimum floorplan.

  1. Core Boundary
    Floorplan defines the size and shape of your chip/block. A top level digital design will have a rectangular/square shape, whereas a sub block may have rectangular or rectilinear shapes. Core boundary refers to the area where you will be placing standard cells and other IP blocks. You may have power routing spaces allocated outside the core boundary. For a full chip, you will also have IO buffers and IO pads placed outside the core boundary.

    In your PnR tool, floorplanning can be controlled by various parameters:

    • Aspect ratio: This is the ratio of width divided by height and determines whether you get a square or rectangular floorplan. An aspect ratio of 1 gives you a square floorplan.
    • Core utilization
      ` Core utilization = (standard cell area+ macro cells area)/ total core area`
      A core utilization of 0.8 means that 80% of the area is available for placement of cells, whereas 20% is left free for routing.
    • Boundary: You can specify a boundary and ask the tool to honour it. This can come in handy when you have an existing boundary from a previous version.When you specify Boundary as the control parameter, both aspect ratio and core utilization are irrelevant. The tool gives you a report of the utilization for the current boundary specified.
    read_pin_pad_physical_constraints ./pins.tdf
    set_fp_pin_constraints -hard_constraints {layer location}  -block_level
    read_def ./boundary.def
    create_floorplan -control_type boundary -start_first_row -flip_first_row \
                     -left_io2core 10 -bottom_io2core 10 \
                     -right_io2core 10 -top_io2core 10
  2. IO Placement/Pin placement
    If you are doing a digital-top design, you need to place IO pads and IO buffers of the chip.Take a reactangular or square chip that has pads in four sides.To start with, you may get the sides and relative positions of the PADs from the designers. You will also get a maximum and minimum die size according to the package you have selected. To place IOs, I use a perl script to place them once I decide on my chip size.

    If you are doing a digital block, you will need to place pins around the boundary to connect to the higher level routing. Cadence tools can use a DEF file or a custom floorplan file to do this. ICC can read in a DEF or a pin placement file to do the SAME.

    DEF extract:

    `DESIGN my_design_lib;
    DIEAREA ( 0 0 ) ( 1914800 1150100 ) ;

    PINS 550 ;
    – sel[1] + NET sel[1] + DIRECTION INOUT
    + LAYER MET3 ( 0 0 ) ( 500 500 )
    + PLACED ( 0 265900 ) N ;


  3. Macro placementOnce you have the size & shape of the floorplan ready and initialized the floorplan, thereby creating standard cell rows, you are now ready to hand place your macros. Do not use any auto placement, I have not seen anything that works. Flylines in your tool will show you the connection between the macros and standard cells or IOs.
      1. Use flylines and make sure you place blocks that connects to each other closer
      2. For a full-chip, if hard macros connect to IOs, place them near the respective IOs
      3. Consider the power straps while placing macros. You can club macros/memories
    1. Creating Power Rings and StrapsThis is a topic worthy of its own article, and I will get to arriving at the number and width of power rings&straps at another post. Let me just now touch upon how to generate the power rings using ICCompiler.
      At this stage, you decide on the trunks that supply power to the core. You also have to make sure that all the hard macros have sufficient rings/straps around it to hook into the PG trunks. As usual, a robust power structure will take iterations and IR drop analysis at a later stage, but a close approximation can be arrived at the initial stages.

      `create_rectangular_rings, create_rectilinear_rings and create_power_straps` are some commands in ICCompiler that will let you create the power network.

83 comments on “Physical Design Flow I : NetlistIn & Floorplanning

  1. Pingback: VLSI Pro – Physical Design Flow IV:Routing

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  3. JINJU P K

    First of all thank you very much for such an article for novice in physical design. I joined in Broadcom for Internship as physical design engineer. And this article helped me a lot. Do you have any other suggestion to read?

  4. ameer

    madam can u xplain what happens/drawbacks if a HARD MACRO/IP is placed at the center of the block which you are working? please give in detailed answer?

  5. JINJU P K

    Hi, why the tool is placing buffers for each ports in our design? Foe each port a buffer will be there near by. What is the need for this?

    1. Sini

      I don’t know which tool you are using, but that is a very good feature to have in P&R. People usually write custom scripts to do that. If you explore, you must be able to change the buffer drive strength etc.

      Why is it needed?– The ports in your digital block is the interface to components outside, say the analog top/other blocks. So you are ensuring that the port can drive these. e.g. if you have a BUFX4 immediately before an o/p port, the next gates outside has that information and the interface guy can either route it to the target gate or add buffers accordingly. Without an STA option in an analog top design, this kind of standardization is needed. Similarly for an input port. An input signal maybe going to say 10 gates. However, by adding a buffer immediately after the port you are ensuring that this can drive all the subsequent gates and the net length is known from that point onwards.

  6. Sarath chandra

    Hi Mam,
    (1) What’s the exact meaning of Coarse Placement?
    (2) How many types of pLacements are there?
    (3) We have different libraries for LVT & HVT & SVT cells.How can the ICC tool recoginse the HVT,LVT and SVT cell libraries?Is there any command or variable to be used to make the tool understand?
    (4) what is channel biasing?

    Thanks in advance

    1. Sini Mukundan Post author

      1. Rough or trial placement.
      2. place_opt is the actual placement command in ICC. It has multiple options. I believe psynopt also is a similar command. I am not sure, but I think place_opt calls psynopt. Try ” help *place* ” in ICC and read the man pages of the commands you find.
      3. I don’t know of any command. Typically naming conventions (_LVT, _SVT etc) are used to distinguish in scripts.
      4. Are you talking about the mosfet channel bias? This is a good resource.
      ‎ Essentially the Vgx, with x starting from the drain terminal is called channel bias.

  7. Sarath chandra

    When i am trying to run placement the icc tool is showing that “Failed to load view node ../../../abc.db”
    How can we fix this type of error?

  8. Rinu Johnson

    Hai mam

    Why do we get empty modules while importing netlist to floorplan and i get a warning of no core in the design….am using cadence SOC encounter tool…what has to be done to rectify it…

    Thanks in advance

    1. Sini Mukundan Post author

      Looks like a problem with your netlist. Open netlist and make sure the top module has all instantiations.

  9. Deepthi Priyanka

    When I am trying to import the design in .ddc format into the icc, it is showing an error message that “Cannot write milkyway for un-uniquified design”
    How to rectify this error. Can anybody of you help me..

    1. Sini Mukundan Post author

      For each technology there are some ballpark figures you go with. Once you get the synthesis area you need to add the overheads due to CTS, optimizations and routing. Say 30% extra from synthesis area is typical for routing using your technology then that’s what you can go with. If it is a block your pin positions will also influence the routability.

      You will need iterations to arrive at an optimum size.

  10. Koushik Mahanta


    How can we know — which I/O ports are connected to which Macros (or standard cells) so that we can group the IO ports at proper locations and have a good Macro placement ? [Flylines didn’t show the I/O connectivity to Macros]

    1. Sini Mukundan Post author

      Which tool are you using?
      Flyline settings should have this option. It does in EDI.

  11. Mukesh Singh

    ENDCAP cells are usually placed at the endings of rows. Why are they required ? Why can’t we just use FILLER cells ? And what is the structural difference between ENDCAP cells and FILLER cells ? Please provide the layout of endcap cells.

    1. Sini Mukundan Post author

      End cap cells are required for certain technologies which require a well ring around your digital circuit. Filler cells have the WELL geometries to fill in the gaps; similarly endcap cells has the well geometry to make a ring around your core and touching the existing well. You don’t really require endcap cells. You just need to draw the ring as specified by the DRC rules. Endcap cells makes this easy and automated. Once you have placed the endcap cells properly, open the layout with well visible and you can see how the ring is formed.

  12. Dwij

    there are only standard cells in the core area with 5% of std.cell utilization(no macros in the design, no blockage issues etc.)but still suppose i get congestion (vertical as well as horizontal). what is the reason for that and how to sort out?

  13. Sini Mukundan Post author

    Feedthrough nets are nets that ‘traverse’ through a hierarchy. e.g., if you have a module dig_top, and if ‘in1’ is an input port and out1 i an o/p port, it is a feedthrough if the only connection is from in1 to out1. i.e

    assign out1 = in1;

    Adding buffers to remove the assign statements is usually done, as the tool have issues with assigns, and also the timing can be constrained.

    1. nagasivakumar

      If the assign statements present in the netlist Tool will do temporary buffers to remove assign statements.
      Could you let me know the difference of assign statements in hierarchical design and flattened design?

  14. Niket

    Can anyone please explain me why do we need to remove assign statements from the netlist in the PD flow…? Its not clear to me.

  15. Syed Dawood

    First of all thank you for all these detailed explanation on PD topics 🙂 Can you please tell me the step by step procedure to design a power grid for a IP/subblock/subchip . It will be very helpful to know 🙂 thank you again .


  16. Swaroop

    Hi Sini,

    I’m doing PD flow using Cadence EDI. When I place the IO buffers and try to run bump assignments and bump routing(LB Layer), the bump assignment and subsequently bump routing does not happen. When is the ideal time to to place the IO buffers? Is it after all the steps in the floor planning stage and just before the placement of the standard cells begins?


    1. Sini Mukundan Post author

      Yes, you are supposed to the bump placement before placement.

      Which commands are you using? If you have bump pad cell, please see if the LEF definitions are correct. (Assuming you are using LEF flow.) It should be type PAD.

  17. Achyuth

    Hi sini,

    Actually how can we estimate the width and height of the die,on what aspects we will decide it ,if we are dealing with a chip level design.I know for block level the top level designer will provide height and width.

    1. Sini Mukundan Post author

      1. Design should fit in the size. A rough estimate at the beginning.
      2. Package selection. Typically this is what determines the die size.
      3. Cost. The aim is to go the lowest size, but if you have a pre-selected package for some reason(say, backward compatibility) then you maybe able to have a bigger size than the optimum.

  18. Yayavaram

    Congratulations, it seems you have great passion for your work. Great doing.
    you are helping many enthusiasts. Best wishes and God bless

  19. vijay

    Hi Sini,

    after floorplan initilization , i found that my IO cells placement reversed . Pad pin is near the core and signal pins are in opposite . what might be the problem.


  20. Amrit Mishra

    Actually my question is related to logical libraries(target and link library) which we give as input during synthesis. we give 3 libraries max.db min.db typ.dp . max is for worst delay (PVT) and min for best delay (PVT) then why we need typ.db as we have already checked the corner cases?
    Thank you in advance

    1. Sini Mukundan Post author

      You are correct if you are going for bc-wc scenarios. I believe OCV may cause a violation in typ corner even if the extreme corners are clean.

  21. Kimch

    Hi. I’m Kim.
    Your comment is very useful.
    I have one question.
    My team(manual top) make phantom cell(Logic block) for TDF file.
    but rectilinear shape is hardful.
    So first, make rectilinear logic block only boundary port exist.
    And export def file by icfb.
    But I don’t know how to make def file by icfb.
    I’ll waiting your reply.
    Best regard.

    1. Sini Mukundan Post author

      I don’t understand the flow you are using.

      Is your requirement to create a DEF file with pin and rectilinear shape for your logic(digital) block from ICFB?

      In that case case, you need to draw a ‘P&R boundary’ in ICFB. Then export DEF. That should have the rectilinear b0qoundary.

  22. badarinath

    Hello mam,
    I have a few questions.
    1) What does FRAM stand for or is it not an acronym?
    2) Why do we check only setup violation at placement and not hold?
    3) What is useful skew?
    4) How to find out the minimum spacing between macros before floorplan

  23. Vik

    Sini- thank you for this excellent overview. One question- I don’t quite understand where DFT/scan/BIST/JTAG insertion occurs. Some ASIC flowcharts say it’s during synthesis, while others point to place&route. I don’t see it mentioned in these physical design overviews, so can I assume it happens during synthesis?

    1. Sini Mukundan Post author

      Yes, in the flows I have followed it happens in synthesis.

      You can reorder the scan in P&R, by giving the chain start and end points. Will need to regenerate the scan patterns.

  24. sekhar

    HI I am very much impressed by this site, and you provided a good content.

    I have doubts on RDL routing, pad cells and io pads. I am not clear about these topics. Could you please provide me any suitable documents or explanation to above topics.


  25. manasa sarovari

    could you please tell me about the link libraries and the target libraries used in ICC(synopsys physical design tool)..

    1. Gautham Lakkur

      Hi Manasa,

      Link Libraries – The hard instantiated macros in the design are usually specified here. these libs are used for linking the design.

      Target Libraries – The standard cell libs from which the logic gates are used to implement the design are specified here. Depending on the design requirement (QoR) various channel length & VT lib types of a particular node can be mentioned here.

  26. manasa sarovari

    thank you for the explaining in detail about floorplanning.. could you tell me something about the partitioning techniques(kerninghan-algorithm, FM, simulated annealing)??? which technique is currently used….

  27. Sini Mukundan Post author

    throughpin is specified when you do not want a pin to be a leaf pin in CTS, but want to trace through the pin for subsequent leaf nodes.
    e.g. — CLK of a flop which shouldn’t be balanced, but which should be traced through to subsequent flops(which should be balanced)

  28. Chetan

    in ICC after doing check library it’s showing missing cell in Logic library =19
    and no of cells with missing or mismatched pins in library=24 what it means is it library problem or something else.

  29. adira

    Can I draw a wire(width being same as the width of a a power stripe) over a specified instance and extend it to nearest power stripe in encounter? This is for solving IR -drop issues.

  30. Anand

    I have doubt regarding macro channel spacing.
    The formula is (no. of pins * metal pitch)/(no. of metal layers/2).
    So in this which metal layer’s metal pitch should be considered. Is it the the top layer which is used for power routing?

    1. Sini Mukundan Post author

      I think you will be OK with the layer of pins used in the macro. It should be able to connect down to complete the routes.(unless pins are in metal1/metal2)

      Using the highest level metal will give you typically higher pitch value, and more routing space, so you can go for it if you can spare the area.

  31. Ashok

    From the area report that i go from synthesis, i added 30% to that area and set the floor plan. How do we know how much core area to set??

    Thanks in advance

    1. Sini Mukundan Post author

      1. Look at how many sequential elements you have — the numbers will influence your clock tree.
      2. How many metal layers do you have?

      30% to start with is OK. Add in the utilization as well. synthesis + 30% for optimization in p&R and any other blockages etc.
      Depending on your metal levels and the process you will be able to chose between 70-90% utilization. So add in that as well.

  32. srivatsan s

    Hi sini,
    what is the difference between physical library and logical library?
    what both of them contains? how it’s different from timing library?
    what is FRAM view and cel view?


    1. Sini Mukundan Post author

      CEL view has the cell layout in its entirety. FRAM view only has pins and blockages & PRBoundary necessary for routing.

  33. Lakshmi

    Got assign statements in the place and route output netlist as I don’t have these kind of statements in synthesis output

    1. Sini Mukundan Post author

      Which tool? There should be an option to buffer assign statements. You need to set it before placement.

  34. Rahul

    you are asking not to auto place macros… what in the case of 80 macros ????Do we need to hand place all those macros

    1. Sini Mukundan Post author


      If you do have a tool that does a good job of auto placing macros, go ahead. I have only worked with 3 pnr tools and all were bad when it came to macro placement.

  35. Shashi Kumar G

    Hello Mam,
    can u provide information regarding number and width calculation of metal rings and straps during fp in detail.

  36. Asmanee

    I’m a fresher in VLSI design and your articles are very useful to understand EDA tools from industry point of view.
    Way to go! Good work 🙂

  37. Anjan Govindaraju

    Hello Sini,

    Your explanantion of key concepts are just too good ! Thanks for clarifying so many of our doubts too !!

    But I could not find any LOGIC SYNTHESIS related detailed explanation of each steps in your website? Can you please point me to it, if there is?

    It would be of really great help since now-a-days PD engineers are expected to know all about Synthesis.


  38. KHY

    Hi Madam
    Is there any difference between Verilog code and Netlist.

    Thank you for the brief introduction

    1. Sini Mukundan Post author

      verilog language can be used to code RTL, which defines the circuit in terms of registers and combinational circuit.

      Once synthesized, you get a netlist which is a combination of cells – Which is again in verilog language.

      Verilog language can also be used to code in a higher level for simulations.


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