# SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence

Multi-clocked sequences are built by concatenating multiple single clocked sequences in different clock domains using following operators.

1. Single delay concatenation operator (##1)
2. zero-delay concatenation operator (##0)

## Single delay concatenation operator (##1)

```sequence mult_seq1;
@(posedge clk1) seq1 ##1 @(posedge clk2) seq2;
endsequence: mult_seq1
```

Match of mult_seq1 starts with a match of seq1 at posedge of clk1 and end with a match of seq2 at posedge clk2. After matching seq1, ##1 moves the time to the nearest strictly subsequent posedge clk2 and then try for seq2 match.

If clk1 and clk2 are identical, the above sequence will be equivalent to the following seq.

```sequence mult_seq1;
@(posedge clk1) seq1 ##1 seq2;
endsequence: mult_seq1
```

## zero-delay concatenation operator (##0)

```sequence mult_seq2;
@(posedge clk1) seq1 ##0 @(posedge clk2) seq2;
endsequence: mult_seq2
```

Match of mult_seq2 starts with a match of seq1 at posedge of clk1 and end with a match of seq2 at posedge clk2. After matching seq1, ##0 moves the time to the nearest possibly overlapping tick of posedge clk2 and then try for seq2 match.

If clk1 and clk2 are identical, the above sequence will be equivalent to the following seq.

```sequence mult_seq1;
@(posedge clk1) seq1 ##0 seq2;
endsequence: mult_seq

sequence mult_seq1;
@(posedge clk1) seq1 && seq2;
endsequence: mult_seq
```

## Restrictions

• Multi-clocked sequence operands cannot be combined with any sequence operators other than ##1 or ##0
Some examples are the following.

```sequence mult_seq2;
@(posedge clk1) seq1 ##2 @(posedge clk2) seq2;  //Illegal !!!!!
endsequence: mult_seq2
```
```sequence mult_seq2;
@(posedge clk1) seq1 and @(posedge clk2) seq2;  //Illegal !!!!!
endsequence: mult_seq2
```
• Empty matches are not allowed for multiclocked sequence operands
This restriction guarantees to have well defined starting and ending clocking events and avoids ambiguity.

```sequence mult_seq;
@(posedge clk1) seq1 ##1 @(posedge clk2) seq3[*0:3]; //Illegal (possibility of an empty match)
endsequence: mult_seq
```

If more than one clock ticks have been allowed at the boundary then the ending clocking event is ambiguous. In other words, if clk1 and clk2 are not identical and if seq3 is an empty match, then there is an ambiguity on the ending clocking event.

```  @(posedge clk1) seq1 ##1 @(posedge clk2) seq3[*0:3]; //Illegal (possibility of an empty match)
endsequence: mult_seq
```
• Multi clocked sequences are useful in verification, if it involves multiple clock domains.